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</o:shapelayout></xml><![endif]--></head><body lang=EN-GB link=blue vlink=purple><div class=WordSection1><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'>Bottom of Page 4526.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'> “LPC Bridge has no interrupt to disable” do not think this is what we both need.<a name="_MailEndCompose"><o:p></o:p></a></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'> (LPC is a group of GPIO pins used as a “low pin count buss”)<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'>Try page 4572..<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'>Good luck; <o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'>Personally I am going to use a SPI I/O Expander chip to capture my 500nSec pulse.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'>If Intel read this why duplicate pages when the only difference between most GPIO Pins is the base addresses.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'>5308 pages at least 25% seem to duplicates.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'>NDA agreements! How do Intel expect us use these chips? We are not expecting design documentation, just programmers reference material. Design , it would be nice if we could read 8 or 16 bits with one instruction. Something the Quark can do.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'>Legacy bridges, the legacy world was bytes or words, I/O as bits is new world.<o:p></o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><span style='font-size:11.0pt;font-family:"Calibri",sans-serif;color:#1F497D;mso-fareast-language:EN-US'><o:p> </o:p></span></p><p class=MsoNormal><b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri",sans-serif'>From:</span></b><span lang=EN-US style='font-size:11.0pt;font-family:"Calibri",sans-serif'> elinux-MinnowBoard [mailto:elinux-minnowboard-bounces@lists.elinux.org] <b>On Behalf Of </b>czq<br><b>Sent:</b> 07 October 2015 16:59<br><b>To:</b> elinux-minnowboard@lists.elinux.org<br><b>Subject:</b> [MinnowBoard] Find GPIO Interrupt Line<o:p></o:p></span></p><p class=MsoNormal><o:p> </o:p></p><div><p class=MsoNormal>Hi there,<o:p></o:p></p><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>I'm reading <i>Intel® AtomTM Processor E3800 Product Family Datasheet</i>, trying to find out the interrupt line of GPIO.<o:p></o:p></p></div><div><p class=MsoNormal>Unlike most other PCI devices, which ususally have an interrupt register at 3c-3fh in its PCI configuration space, GPIO/LPC has a weird (at least to me) configuration space (page 4525)... I don't know how to find its interrupt line.<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>In the GPIO chapter, I can see it has memory mapped registers called Direct Interrupt Multiplexer. But I can't really understand the description. It also says that more details are available in <i>VLV2_GPIO_configuration_primer presentation.</i><o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>So does anyone know where I can find the <i>VLV2_GPIO_configuration_primer</i> presentation (I searched a lot but no luck...).<o:p></o:p></p></div><div><p class=MsoNormal>Or any thoughts and hints about how to find the interrupt line?<o:p></o:p></p></div><div><p class=MsoNormal><o:p> </o:p></p></div><div><p class=MsoNormal>Thanks a lot!<o:p></o:p></p></div><div><p class=MsoNormal>Tom.<o:p></o:p></p></div></div><p class=MsoNormal><o:p> </o:p></p><div class=MsoNormal><hr size=3 width=300 style='width:150.0pt' align=left></div><p class=MsoNormal>View this message in context: <a href="http://minnowboard.57273.x6.nabble.com/Find-GPIO-Interrupt-Line-tp1947.html">Find GPIO Interrupt Line</a><br>Sent from the <a href="http://minnowboard.57273.x6.nabble.com/">MinnowBoard mailing list archive</a> at Nabble.com.<o:p></o:p></p></div></body></html>