[MinnowBoard] Early serial output
maurice.ma at intel.com
Sat Jan 24 01:42:22 UTC 2015
Glad to know you have it working now.
Regarding to the FSP execution environment, it has a document called FSP EAS. Did you get a chance to look into it? It talks about the API calling assumptions.
Putting GDT in the temporary memory could be the problem. FspInit will initialize the memory, migrate your temporary memory into system memory and then tear down the temporary memory. At the end the FspInit will call back into the ContinuationFunc using your old bootloader GDT, which is not valid any more since temporary memory is gone.
For the limitations that FSP placed on the bootloader, can you give more details ? What are those limitations? We definitely want to hear those feedbacks and if possible, make some improvements in the new release.
From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
Sent: Friday, January 23, 2015 5:02 PM
To: Ma, Maurice
Cc: MinnowBoard Development and Community Discussion; Hawley, John
Subject: Re: [MinnowBoard] Early serial output
On 23 January 2015 at 16:05, Ma, Maurice <maurice.ma at intel.com> wrote:
> Hi, Simon,
> For the Baytrail built-in serial port initialization, it should not be very difficult. Everything is in the coreboot src/soc/intel/fsp_baytrail/romstage/uart.c file. Once it is done, you just need to call the "console_init()" function in coreboot.
Yes, I wonder if I just needed to run 'make clean'. It started working and I didn't change anything.
> "SerialDebugPortAddress" is a feature we provided in FSP to display some debug information. It is available in some of the FSP implementations, such as SharkBay FSP. However, for Baytrail, due to the IBB 127K size restriction, we do not have enough space to put debug information inside the FSP binary. So this feature is not available in BayTrail FSP.
OK thanks for explaining it. It would be good if it could return with an error instead of locking up.
> If you encounter a FspInit() hang, in most of the cases it is related to your memory down configuration parameters. Did it occur on MinnowBoardMax or on a different board? Can you verify the parameters are correct?
The problem may be that I had the GDT in temporary RAM, or perhaps that I had a non-standard GDT (U-Boot sets fs: to point to a special place). It would help to have more details about the execution environment that the FSP needs. The documentation doesn't really talk about these sorts of things. For now I am doing the FSP init much earlier than I would like.
> To enable U-Boot is should be very straight forward. You need to configure the file under u-boot properly ( include\configs\coreboot.h). And then you can do a "make coreboot-x86_config" and "make". The generated u-boot ELF file can be used as the coreboot payload directly.
Actually I was referring to getting U-Boot running 'bare' on the board. That seems to work now, so I'll see if the Coreboot->U-Boot side works too.
Separately, I'm not happy with the limitations the FSP places on the boot loader. My implementation is quite poor. Should I send such feedback to the list, or is no one interested?
Anyway, I'm happy to have it running.
> -----Original Message-----
> From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
> Sent: Wednesday, January 21, 2015 9:13 PM
> To: MinnowBoard Development and Community Discussion
> Cc: Hawley, John; Ma, Maurice
> Subject: Re: [MinnowBoard] Early serial output
> On 21 January 2015 at 21:52, Simon Glass <sjg at chromium.org> wrote:
> > Hi Maurice,
> > On 21 January 2015 at 13:18, Simon Glass <sjg at chromium.org> wrote:
> >> Hi Maurine,
> >> On 20 January 2015 at 18:02, Ma, Maurice <maurice.ma at intel.com> wrote:
> >>> Hi, Simon,
> >>> Just want to make sure that you are talking about the MinnowBoard (TunnelCreek + TopCliff), not MinnowBoard Max (Baytrail), right?
> >>> For MinnowBoard Max, I have tested and the early serial port does work before the FSP API call.
> >>> For MinnowBoard, the serial port is from UART0 on TopCliff(EG20T). In order to enable early console in coreboot,
> >>> you need to initialize the TopCliff UART 0 and then call console_init() in romstage after FSP TempRamInit() and before FspInit().
> >>> The standard linux UART driver for EG20T is open, you can refer to :
> >>> http://lxr.free-electrons.com/source/drivers/tty/serial/pch_uart.c
> >>> You just need to implement the standard RX and TX function for Coreboot. It should be straight forward.
> >>> Please note, since the EG20T UART is on PCI bus and the PCI bus is not enumerated yet at early boot stage. So you need to assign temporary bus and PCI MMIO resource to the bridges and the UART controller before accessing the UART registers.
> >> Yes i it Minnowboard Max. It sounds like you are saying I should
> >> get serial output early in romstage, but I don't. Do I need to
> >> enable something?
> > Just to follow up, I got this working. It seems there is quite a
> > long list of init to be done to get the serial working. But I have
> > early output running now. Thanks for your help.
> OK, one more follow-up. I'd like to get U-Boot running now if I can.
> The FSP is hanging in FspInitEntry. Is there a way to turn on serial debug to see what is going on? Is there any other debug method available? I can't see post codes on this board and it doesn't seem to return an error code.
> I see some fields called 'SerialDebugPortAddress' in some FSPs, but not in the header files for gold v3.
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