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Hi.<br>
<br>
As i wrote earlier i built my own board based on MAX2. On first
board revision i specially dont touch anything and just copy MAX2
pcb routing.<br>
<br>
On second revision i connected some unused GPIOS to various
peripherals and also prepare board to trying 4GB memory config by
adding following schematic changes:<br>
<br>
On DDR3 chips side:
<p><img src="cid:part1.086D250C.7EFA9788@mail.ru" alt=""></p>
<p>On Atom side:</p>
<p><img src="cid:part2.44633720.EA3279CD@mail.ru" alt=""></p>
<p><br>
</p>
<p>The problem is that MemoryInit.efi detects different dram speed.</p>
<p>On first board revision as on MAX2:<br>
</p>
<p><b>MemoryInit.efi</b><b><br>
</b><b>PROGRESS CODE: V3020002 I0</b><b><br>
</b><b><font color="#ff0000">Reg_EFF_DualCH_EN = 0x200301C0</font>.</b><b><br>
</b><b>Buffer size brefore add 165B, after adjust 1668.</b><b><br>
</b><b>MRC Parameters not valid. status is 8000000E</b><b><br>
</b><b>Set MRC paramaters for MinnowBoard Max. </b><b><br>
</b><b>MmioConf0[0xFED0E220], MmioPadval[0xFED0E228]</b><b><br>
</b><b>Gpio_S5_5 value is 0x3</b><b><br>
</b><b>Determine the memory size is [2GB]</b><b><br>
</b><font color="#ff0000"><b>DRAM_Speed is 1066MHz!</b></font><b><br>
</b></p>
<p>On second board revision:</p>
<p><b>MemoryInit.efi</b><b><br>
</b><b>PROGRESS CODE: V3020002 I0</b><b><br>
</b><b>POSTCODE=<43B3></b><b><br>
</b><font color="#ff0000"><b>Reg_EFF_DualCH_EN = 0x100301C0.</b></font><b><br>
</b><b>Buffer size brefore add 165B, after adjust 1668.</b><b><br>
</b><b>MRC Parameters not valid. status is 8000000E</b><b><br>
</b><b>Set MRC paramaters for MinnowBoard Max. </b><b><br>
</b><b>MmioConf0[0xFED0E220], MmioPadval[0xFED0E228]</b><b><br>
</b><b>Gpio_S5_5 value is 0x3</b><b><br>
</b><b>Determine the memory size is [2GB]</b><b><br>
</b><font color="#ff0000"><b>DRAM_Speed is 1333MHz!</b></font></p>
Can someone from intel explain what Reg_EFF_DualCH_EN actually mean?<br>
<br>
May be there is some "hidden" gpio configs used?<br>
<br>
Finally why MemoryInit detects 1333Mhz clock speed?<br>
<br>
I tried to bypass this issue using SPD but it does not work as i
wrote in previous post.<br>
<br>
P.S. DDR3 chips is same on both boards. Routing is slightly differs
due to new connected signals and four resistors but it all fits ddr3
routing rules. Length match etc.<br>
<br>
Thanks.<br>
<br>
Grigory<br>
<p><br>
</p>
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