[MinnowBoard] DDR3 Memory clock detection by MemoryInit.efi

[Grigory V. Korotov]

Hi.

As i wrote earlier i built my own board based on MAX2. On first board 
revision i specially dont touch anything and just copy MAX2 pcb routing.

On second revision i connected some unused GPIOS to various peripherals 
and also prepare board to trying 4GB memory config by adding following 
schematic changes:

On DDR3 chips side:

On Atom side:


The problem is that MemoryInit.efi detects different dram speed.

On first board revision as on MAX2:

*MemoryInit.efi**
**PROGRESS CODE: V3020002 I0**
**Reg_EFF_DualCH_EN = 0x200301C0.**
**Buffer size brefore add 165B, after adjust 1668.**
**MRC Parameters not valid. status is 8000000E**
**Set MRC paramaters for MinnowBoard Max. **
**MmioConf0[0xFED0E220], MmioPadval[0xFED0E228]**
**Gpio_S5_5 value is 0x3**
**Determine the memory size is [2GB]**
**DRAM_Speed is 1066MHz!**
*

On second board revision:

*MemoryInit.efi**
**PROGRESS CODE: V3020002 I0**
**POSTCODE=<43B3>**
**Reg_EFF_DualCH_EN = 0x100301C0.**
**Buffer size brefore add 165B, after adjust 1668.**
**MRC Parameters not valid. status is 8000000E**
**Set MRC paramaters for MinnowBoard Max. **
**MmioConf0[0xFED0E220], MmioPadval[0xFED0E228]**
**Gpio_S5_5 value is 0x3**
**Determine the memory size is [2GB]**
**DRAM_Speed is 1333MHz!*

Can someone from intel explain what Reg_EFF_DualCH_EN actually mean?

May be there is some "hidden" gpio configs used?

Finally why MemoryInit detects 1333Mhz clock speed?

I tried to bypass this issue using SPD but it does not work as i wrote 
in previous post.

P.S. DDR3 chips is same on both boards. Routing is slightly differs due 
to new connected signals and four resistors but it all fits ddr3 routing 
rules. Length match etc.

Thanks.

Grigory


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